one hot assignment

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9.6 ONE-HOT ENCODING METHOD

One-hot encoding is an alternative state assignment method which attempts to minimize the combinational logic by increasing the number of flip-flops. The goal of the method is to try to reduce the number of connections between the logic gates in the combinational circuit of the FSM. The presence of more gate interconnections results into longer propagation delays and a slower FSM. Since the propagation delay through the flip-flops is faster, FSMs require fewer logic gates but not necessarily fewer flip-flops.

Figure 9.26 Logic Implementation of the FSM in Figure 9.24

One-hot encoding assigns one flip-flop for each state. For example, a finite-state machine with N states requires N flip-flops. The states are assigned N -bit binary numbers; where only the corresponding bit position is equal to 1, the remaining bits are equal to0. For example, in a finite-state machine with four states S 0 , S 1 , S 2 , and S 3 , the states are assigned the binary values 0001, 0010, 0100, and 1000, respectively. Notice that only one bit position is equal to 1; the other bits are all equal to 0. The reamaining 12 binary combinations are assigned to don't-care states. Consider the Mealy-type finite-state machine described by the state diagram shown in Figure 9.19 . The state diagram has three states: S 0 , S 1 , and S 2 . One-hot encoding assigns the binary number values 001, 010, and 100 ...

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One-hot State Machine in SystemVerilog – Reverse Case Statement

Finite state machine (FSM) is one of the first topics taught in any digital design course, yet coding one is not as easy as first meets the eye. There are Moore and Mealy state machines, encoded and one-hot state encoding, one or two or three always block coding styles. Recently I was reviewing a coworker’s RTL code and came across a SystemVerilog one-hot state machine coding style that I was not familiar with. Needless to say, it became a mini research topic resulting in this blog post.

When coding state machines in Verilog or SystemVerilog, there are a few general guidelines that can apply to any state machine:

• If coding in Verilog, use parameters to define state encodings instead of ‘define macro definition. Verilog ‘define macros have global scope; a macro defined in one module can easily be redefined by a macro with the same name in a different module compiled later, leading to macro redefinition warnings and unexpected bugs.
• If coding in SystemVerilog, use enumerated types to define state encodings.
• Always define a parameter or enumerated type value for each state so you don’t leave it to the synthesis tool to choose a value for you. Otherwise it can make for a very difficult ECO when it comes time to reverse engineer the gate level netlist.
• Make curr_state and next_state declarations right after the parameter or enumerated type assignments. This is simply clean coding style.
• Code all sequential always block using nonblocking assignments (<=). This helps guard against simulation race conditions.
• Code all combinational always block using blocking assignments (=). This helps guard against simulation race conditions.

SystemVerilog enumerated types are especially useful for coding state machines. An example of using an enumerated type as the state variable is shown below.

Notice that enumerated types allow X assignments. Enumerated types can be displayed as names in simulator waveforms, which eliminates the need of a Verilog trick to display the state name in waveform as a variable in ASCII encoding.

One-hot refers to how each of the states is encoded in the state vector. In a one-hot state machine, the state vector has as many bits as number of states. Each bit represents a single state, and only one bit can be set at a time— one-hot . A one-hot state machine is generally faster than a state machine with encoded states because of the lack of state decoding logic.

SystemVerilog and Verilog has a unique (pun intended) and efficient coding style for coding one-hot state machines. This coding style uses what is called a reverse case statement to test if a case item is true by using a case header of the form case (1’b1) . Example code is shown below:

In this one-hot state machine coding style, the state parameters or enumerated type values represent indices into the state and next vectors. Synthesis tools interpret this coding style efficiently and generates output assignment and next state logic that does only 1-bit comparison against the state vectors. Notice also the use of always_comb and always_ff SystemVerilog always statements, and unique case to add some run-time checking.

An alternate one-hot state machine coding style to the “index-parameter” style is to completely specify the one-hot encoding for the state vectors, as shown below:

According to Cliff Cummings’ 2003 paper , this coding style yields poor performance because the Design Compiler infers a full 4-bit comparison against the state vector, in effect defeating the speed advantage of a one-hot state machine. However, the experiments conducted in this paper were done in 2003, and I suspect synthesis tools have become smarter since then.

State machines may look easy on paper, but are often not so easy in practice. Given how frequently state machines appear in designs, it is important for every RTL designer to develop a consistent and efficient style for coding them. One-hot state machines are generally preferred in applications that can trade-off area for a speed advantage. This article demonstrated how they can be coded in Verilog and SystemVerilog using a unique and very efficient “reverse case statement” coding style. It is a technique that should be in every RTL designer’s arsenal.

What are your experiences with coding one-hot state machines? Do you have another coding style or synthesis results to share? Leave a comment below!

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14 thoughts on “One-hot State Machine in SystemVerilog – Reverse Case Statement”

I am enjoying reading your blog, but I believe you are missing something from your one-hot reverse-case example above. In Cliff’s paper, the enumerated type is used as an index to a vector – you neglected to copy this part over. I believe the correct code would look like this:

enum { IDLE = 0, READ = 1, DLY = 2, DONE = 3 } state_index_t;

logic [3:0] state, next;

with the vector declaration in place the rest of the example above should work OK.

Hi John, thanks for your comment! You’re correct that in Cliff’s paper the enumerated type is used as an index into the one-hot vector. In my original code above I was sloppy and mixed the value of the enumerated type (0, 1, 2, 3) with the type itself. While I did test the original code and it simulated correctly, I’m sure a linting tool would give a warning about the improper usage. I have made a correction to the code above.

Great post. I have seen improved performance with one hot reverse case statements as well. One comment I would have is that the default assignment for “next” should be a valid case especially since we don’t have a default case statement. In the case of a bit being flipped because of some rare condition you’ll be able to recover. Something like this:

// Combinational next state logic always_comb begin next = ‘0; next[IDLE] = 1’b1; // ADDED unique case (1’b1) state[IDLE] : begin if (go) begin next = ‘0; // ADDED next[READ] = 1’b1; end else begin next = ‘0; // ADDED next[IDLE] = 1’b1; end end

Thanks, Amol, for your suggestion. I understand your reasoning to have a valid case (like IDLE) be the default transition for safety. Personally I don’t code that way as I think a bit flip anywhere in the chip is considered fatal, and even if the affected state machine returns to IDLE, it will likely have become out of sync with other logic and state machines. However, I have coworkers who code in the way you suggested as well.

There is a subtle point that may cause your code to not behave in the way intended. Due to the use of “unique case” in the code, I think for any unspecified cases (e.g. if a bit flip causes the state vector to become 4’b0000; 4’b0000 is not a case that is listed in the case statement), the synthesis tool is free to infer any logic (specifically to the “next” vector), so there’s no guarantee the default “next[IDLE]=1’b1” wouldn’t be overridden by other logic the synthesis tool inferred. See my post on SystemVerilog unique keyword.

Interesting. I had a “typo” in my code recently that caused the case_expression to be one not listed in the case statement and I did observe odd behavior from what I would have expected. So I guess having the default “next[IDLE]=1’b1” is probably not that useful here. 🙂

This is a synthetic example I would assume but want to get your feedback on preserving X-propagation. Bugs in the state machine next state logic or outside the state machine driving the input signals “go” and “ws” can be hidden by the current way of coding (using if-else and also default assigned to 0). Killing x-prop can cause “simulation vs. synthesis mismatch”, which can be pretty fatal. Consider this improvement:

// Combinational next state logic always_comb begin //next = ‘0; // Comment out; see added default in case statement instead unique case (1’b1) state[IDLE] : begin // Ensures x-prop if go === x next[READ] = go == 1’b1; next[IDLE] = go == 1’b0; end state[READ] : next[ DLY] = 1’b1; state[ DLY] : begin // Ensures x-prop if ws === x next[DONE] = ws == 1’b0; next[READ] = ws == 1’b1; end state[DONE] : next[IDLE] = 1’b1; // Add default to propagate Xs for unhandled states or if state reg went X itself default: next <= 'x; endcase end

Hi VK, thanks for your comment! When you say the code “kills x-prop”, I think you mean that if “ws” or “go” input has the value of X, then the “if(x)-else” coding style will take on the “else” case, rather than also corrupting the outputs (in this case the “next” vector)? Yes you’re right, and I’ll admit I’ve coded this kind of bug before! Recently our team has turned on the Synopsys VCS x-propagation feature to detect this kind of problem. It corrupts the output even with this “if-else” coding style (see my post on x-prop ). If that’s not available, then yes, the code you propose will also do the job. Previously I also coded a “default: next <= 'x" in my state machines, but the RTL linting tool we use complains about this, so I've moved away from this style. VCS x-prop will also catch this kind of problem.

I just realized you are not driving every bit of “next” in the case statement, so you would need to have the default next = ‘0 at the beginning as you did originally. That would not kill x-prop anyways since the default in the case statement would override it if needed.

Hello Jason, Thanks for the post. It really helped me to understand more about OneHot FSMs. The statement on Cliff’s paper in 2003 is not entirely true. we can handle that case by adding a unique key word. In the meantime concern raised by VK is great and worth looking into. with both of this I would like you to consider the following code which will give you the same synthesis result. Advantages being 1) state vector is enum, hence waveform visualization is better 2) does propagate x, in case FSM assignment is buggy 3) simpler and easy to read

typedef enum logic [3:0] { IDLE = 4’b0001, READ = 4’b0010, DLY = 4’b0100, DONE = 4’b1000, SX = 4’x } state_t; state_t state, next;

// Sequential state transition always_ff @(posedge clk or negedge rst_n) if (!rst_n) state <= IDLE; else state <= next;

// Combinational next state logic always_comb begin next = SX; unique case (state) IDLE : begin if (go) next = READ; else next = IDLE; end READ : next = DLY; DLY : begin if (!ws) next = DONE; else next = READ; end DONE : next = IDLE; endcase end

// Make output assignments always_ff @(posedge clk or negedge rst_n) …

Thanks for your comments! Yes I had been intending to make an update to this page for while, especially about your first point on waveform display of the state vector. After simulating my coworker’s code in the original coding style, I also realized simulators do not visualize state vectors written this way very well. I would agree that specifying the one-hot state encoding in the enum type should be equivalent and will display better. Your proposed code is indeed how I would write a one-hot state machine using SystemVerilog today!

Hi Jason Reffering to the last comment by shailesh, do you still suggests using “reverse case method” for FSM ? is it worth the less-readable code? or that shailesh’s code will do the same w/o infers the full bit comparison? this code is much more initiuative, but what about performence?

I have not had a chance to look closely at the synthesized netlist of a one-hot encoded state machine written with enumerated type and regular case statement. I believe with today’s compiler technology it should synthesize the same as the reverse case statement method (i.e. optimized to do single state bit comparisons). I coded my most recent design this way based on this belief. I’ll let you know when I can verify exactly the gates that Design Compiler synthesized 🙂

Thanks for the article, Jason. Your articles have helped answer many questions I’ve had. My colleague and I were discussing about this recently and a question came up – Are reverse case statements useful at all in plain Verilog (not System Verilog) if one isn’t allowed to use synthesis pragmas such as ‘parallel_case’? Unlike System Verilog, Verilog doesn’t have the ‘unique’ keyword.

Put in another way, the question is what really happens when one codes a reverse case statement in Verilog with no ‘parallel_case’ directive. Does synthesis assume that the input to the case-statement is not parallel and hence not one-hot and hence infer priority logic? I’d love to hear your thoughts.

I think if coded correctly, the reverse case statement FSM coding style should automatically create a case statement that is parallel, without requiring the ‘parallel_case’ directive. Since each state is represented by a unique number, each case expression is effectively comparing 1 unique register bit against 1’b1. Therefore no overlap between the different case expressions should be possible, which matches the definition of parallel case.

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Chapter: Digital Logic Circuits : Asynchronous Sequential Circuits and Programmable Logic Devices

Using a one hot state assignment.

USING A ONE HOT STATE ASSIGNMENT

When designing with PGAS4, we should keep in mind that each logic cell contains two flip flops. This means that it may not be important to minimize the number of flip flops used in the design. Instead, we should try to reduce the number of logic cells used and try to reduce the interconnections between cells. In order to design faster logic, we should try to reduce the number of cells required to realize each equation. Using one hot state assigning will often help to accomplish this.

The one hot assignment uses one flip flop for each state, so a state machine with N states requires N flip flop. Exactly one flip flop is set to l in each state. For example a system with four (To T 1 , T 2 and T 3 ) could use four flip flop (O 0 , Q 1 , Q 2 and Q 3 ) with the following state assignment.

The other 12 combinations are not used.

We can write next state and output equations by inspection of the graph or by tracking link parts on an SM chart consider the partial state graph . The next state equation for flip flop Q3 could be written as.

However since Q=1 implies Q1=Q2=Q3=0 the Q1=Q2=Q3 term is redundant and can be eliminated, similarly, all the primed state variables can be eliminated from the other terms, so the next state equation reduces to.

Note that each contains exactly one state variable. similarly, each term in each output equation contains exactly one state variable.

When a one hot assignment is used, the next state equation for each flip flop will contain one term for each are leading into the corresponding state (or for each link path leading into the state). In general, each term in every next state equation and in every output equation will contain exactly one state variable. The one hot state assignment for asynchronous networks is similar to that described above, but a “holding term” is required for each next state equation.

When a one hot assignment is used, resetting the system requires that one flip flop be set to 1 instead of resetting all flip flops to 0. If the flip flops used do not have a preset input (as in the case for the xilnx 3000 series), then we can modify the one hot assignment by replacing Q 0 and Q 0 ’ throughout. For the assignment, the modification is

And the modified equations are:

Another way to solve the reset problem without modifying the one hot assignment is to add an extra term to the equation for the flip flop, which should be 1 in the starting state. As an example, we use the one hot assignment given in (6-6) for the main dice game control. The next state equation for Q O is

If the system is reset to state 0000 after power-up, we can add the term Q 0 ’Q 1 ’Q 2 ’Q 3 ’ to the equation for Q 0 . Then, after the first clock the state will change from 0000 and 1000 (T0), Which is the correct starting state.

In general, both an assignment with a minimum number of state variables and a one hot assignment should be tried to see which one leads to a design with the smallest number of logic cells. Alternatively, if speed of operation is important, the design that leads to the fastest logic should be chosen. When a one hot assignment is used, more next state equations are required, but in general both the next state and output equation will contain fewer variables. An equation with fewer variable generally requires fewer logic cells to realize. Equations with five or fewer variables require a single cell. As seen in figure, an equation with six variables require cascading two cells, an equation with seven variables may require cascading three cells etc. The more cells cascaded, the longer the propagation delay, and the slower the operation.

STAT ASSIGNMENT RULES:  A set of heuristic rules that attempts to reduce the cost of the combinational logic in a finite state machine.

ONE HOT STATE ASSIGNMENT: State assignment uses one flip flop for each state, so a state machine with N states requires N flip flops.

1.   Reduce the following state table to the minimum number of states using successive partitioning method.

2.   Reduce the following state table to the minimum number of states using implication chart method.

3.   Use the heuristic rule on page 4 to make compact state assignment. Assign state A to “000”.

4.   Implement the following state using D flip flop and gates. Use a one hot assignment and write down the logic equations by inspecting the state table. Let S 0 =001, S 1 =010, and S 2 =1000.

5.   Repeat problem 1 using the implication chart.

6.   Repeat problem 2 using the successive partitioning method.

7.   Implement the state of problem 3 using one hot state assignment. Assume A=00000001, B=00000010, through H=10000000.

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Encoding the States of a Finite State Machine in VHDL

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This article will review different encoding methods that can be used to implement the states of an FSM.

Another AAC article,  Implementing a Finite State Machine in VHDL , discusses how to implement a finite state machine (FSM) in VHDL .

This article will review different encoding methods that can be used to implement the states of an FSM. We’ll see that, for a given state diagram, the state encoding method can reduce the power consumption of the FSM or increase its clock frequency.

The State Diagram Representation of an FSM

We can use a state diagram to represent the operation of a finite state machine (FSM). For example, consider the state diagram shown in Figure 1. This FSM has eight states: idle , r1 , r2, r3, r4, c, p1, and p2 . Also, it has one input, mem , and one output, out1 . Based on the diagram, the FSM will choose its next state for the upcoming clock tick.

Figure 2 shows the block diagram that can be used to implement the FSM of Figure 1. There are n memory elements, shown inside the dashed box, to store the current state of the system. The box labeled “Logic to Generate the Next State” is a combinational circuit that uses the outputs of the flip-flops (FF) and the system inputs to determine the next state of the system.

This next state will be loaded into the set of FFs at the next clock tick. The box labeled “Logic to Generate the Outputs” receives the current state of the system and generates the output signals. Note that, since the “Logic to Generate the Outputs” is driven only by the state of the system (and not by the inputs), we have a Moore state machine .

Binary Encoding to Implement an FSM

In Figure 1, we have eight different states. How many flip-flops do we need to represent these eight states?

To represent eight states, we need at least three bits. Table 1 shows one possible way of encoding these states; this approach is called binary encoding.

This representation leads to the block diagram shown in Figure 3.

Assume that the three-bit string Q3Q2Q1 represents the three bits of Table 1. For example, when the state of the FSM is r3 , we have Q3Q2Q1=“011”. Figure 3 depicts three capacitors (Cpar1, Cpar2, and Cpar3). These capacitors serve as lumped-element representations of parasitic capacitance that is present in the circuit. This parasitic capacitance is introduced by the circuit interconnections and by the input stages of the combinational circuits that generate the next state and the outputs.

Let’s examine Figure 1 and Figure 3 more closely. According to the state diagram in Figure 1, for mem=1 , each clock tick will make the FSM go from one state to another one. The states are represented by the three flip-flops in Figure 3, and thus with each clock tick, the value of Q3Q2Q1 changes. This means that at least one of the Cpar1/Cpar2/Cpar3 capacitances will need to be charged or discharged. For example, consider the case in which the FSM starts from the state Idle and, after several clock ticks, reaches the state p2 . In this case, the capacitor Cpar1 will be charged four times (see Table 1). Similarly, Cpar2 and Cpar3 will be charged two times and one time, respectively.

Current is consumed every time a capacitor must be charged. So, part of the power consumed by the circuit of Figure 3 originates from charging the parasitic capacitances that are seen at the output of the FFs. How can we reduce the power consumption of this circuit? One way would be to reduce the number of times that we must charge the parasitic capacitance. Can we rearrange the three-bit assignment of Table 1 so as to reduce the number of transitions at the FF outputs? This is, in fact, possible, and the solution, called Gray encoding , is used in Table 2.

Gray Encoding Can Reduce Power Consumption

With the Gray code of Table 2, only one bit changes when moving between adjacent states. Now, when the FSM goes from the state Idle to the state p2 , the least significant bit will be charged two times and the second and third bits will be charged only once. (Compare this to the previously required four, two, and one charging events, as discussed above.) Thus, we can use Gray encoding to reduce the power consumption of the FSM.

Gray encoding is great for the FSM in Figure 1 because, for a given state, the next state of the system is known. However, most of the time, we don’t know the next state of the system. For example:

Figure 4. A state diagram that can use the Gray encoding. Image courtesy of Low-Power CMOS Circuits .

In Figure 4, depending on the value of the inputs, the state after S29 can be either S32 or S30. For such cases, we should first determine which path has a higher probability. Then, we can set up our Gray encoding according to the higher-probability path.

Gray Encoding Can Reduce Glitches

As discussed above, Gray encoding can be used to achieve a lower-power design. Another application of this encoding is in protecting asynchronous outputs from glitches. For example, assume that we are using the schematic of Figure 5 to produce the output out1 in the state diagram of Figure 1. This figure assumes that binary encoding is used to represent the states of the FSM.

Now, consider the waveforms shown in Figure 6, which correspond to a state change from p2 (111) to idle (000).

When the system is at p2 , out1 is high. At t1 , the state changes to Idle . After the time delay of the two-input AND gate, the node n2 will be zero at t2 . A little bit later, at t4 , the node n1 will go high. Note that the delay of n1 is assumed to be longer than that of n2 because n1 is produced by a three-input AND gate placed after NOT gates.

As shown in Figure 6, the final value of out1 will be one (at t5 ); however, there is an unnecessary transition from high to low at t3 . In circuits such as the one in Figure 5, the unnecessary transition occurs because binary encoding allows multiple bits to change at the same time. With Gray encoding, only one bit changes when moving between adjacent states, and thus glitches are less common.

We have seen that appropriate state assignment can reduce the power consumption of an FSM and make its asynchronous outputs resilient to glitches. There is another state assignment method, namely, one-hot encoding, which can simplify the "Logic to Generate the Outputs" and "Logic to Generate the Next State" blocks in Figure 2. With these two blocks simplified, we can generate the FSM outputs and next state faster. The next section discusses this encoding in more detail.

One-Hot Encoding

Note that in one clock period, the combinational circuits of Figure 2 (i.e., the “Logic to Generate Outputs” and “Logic to Generate the Next state” circuits) should produce their outputs so that the FSM is ready to move to the next state with the upcoming clock tick.

One-hot encoding makes these combinational circuits simpler, which reduces propagation delay, which in turn makes the FSM compatible with higher clock frequencies. The trade-off is that one-hot encoding increases the number of FFs used to store the state of the system. For example, whereas binary and Gray encoding use only three FFs to represent the eight states of Figure 1, one-hot encoding utilizes eight FFs (i.e., one flip-flop per state).

Table 3 shows the one-hot encoding for our eight-state FSM.

Why does this make the combinational circuits of the FSM simpler? Because with binary and Gray encoding, we need to use logic gates to “decode” the 3-bit representation into one of the eight states, whereas with one-hot encoding there is nothing to decode—the state corresponds directly to the one bit that is “hot”.

Which State Assignment Is Optimal?

There are some other state encoding options but, in practice, we generally use one of the three encodings discussed above, i.e., binary, Gray, or one-hot.

The question remains: How should we choose the best encoding for a given FSM?

Obtaining optimal state assignment for an FSM is a difficult problem and you can find the theory of this optimization in textbooks such as Synthesis of Finite State Machines: Logic Optimization and Synthesis of Finite State Machines: Functional Optimization . In practice, FPGA synthesis tools can utilize proprietary optimization algorithms to arrive at an efficient implementation of an FSM. If you set the XST (Xilinx Synthesis Technology) fsm_encoding option to “ auto ”, the software will select the best encoding for each FSM in your design.

As an example, consider the state diagram shown in Figure 7.

The VHDL description of the FSM in Figure 7 is as follows:

Using XST to synthesize this code, we obtain the following synthesis log:

=========================================================================

*                       Advanced HDL Synthesis                          *

Analyzing FSM for best encoding.

Optimizing FSM on signal with one-hot encoding.

-------------------

State | Encoding

idle  | 00000001

r1    | 00000010

r2    | 00000100

r3    | 00001000

r4    | 00010000

c     | 00100000

p1    | 01000000

p2    | 10000000

As you can see, XST’s optimization algorithms chose one-hot as the best encoding technique. If you want to choose your encoding method instead of relying on the synthesizer, you can do this via the fsm_encoding option.

• With the Gray code, only one bit changes when moving between adjacent states. As a result, this encoding technique can reduce the power consumption of an FSM. Moreover, the Gray encoding makes the asynchronous outputs of an FSM resilient to glitches.
• One-hot encoding simplifies the "Logic to Generate the Outputs" and "Logic to Generate the Next State" blocks in Figure 2. With these two blocks simplified, we can generate the FSM outputs and next state faster.
• Obtaining optimal state assignment for an FSM is a difficult problem but, in practice, we can use FPGA synthesis tools with proprietary optimization algorithms to arrive at an efficient implementation of an FSM.
• If you set the XST fsm_encoding option to “auto”, the software will select the best encoding for each FSM in your design.

To see a complete list of my articles, please visit this page .

Related Content

• Implementing a Finite State Machine in VHDL
• Creating Finite State Machines in Verilog
• Sequential VHDL: If and Case Statements
• Concurrent Conditional and Selected Signal Assignment in VHDL
• The Initial State of Finite State Machines and the Memory Debate
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• finite state machine
• programmable logic
• one-hot encoding

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Best Practices for One-Hot State Machine, coding in Verilog

There are 3 main points to making high speed state machines by one-hot encoding:

• Use 'parallel_case' and 'full_case' directives on a 'case (1'b1)' statement
• Use state[3] style to represent the current state
• Assign next state by:
• default assignment of 0 to state vector
• fully specify all conditions of next state assignments, including staying in current state.

Also, these points are also recommended:

• Separate the code for next state assignment from output logic/assignments.
• Use parameters to assign state encoding (or `define)
• use continuous assignments,
• set/reset at specific conditions, holding value at all other times

(the designer should choose based on complexity of generated logic)

Simple example:

reg [2:0]  state ; parameter  IDLE=0, RUN=1, DONE=2 ; always @ (posedge clock or negedge resetl)   if ( ! resetl) begin     state <= 3'b001 ;     out1 <= 0 ;   end   else begin state <= 3'b000 ; case (1'b1) // synthesis parallel_case full_case   state[IDLE]: if (go)   state[RUN] <= 1 ; else   state[IDLE] <= 1 ;

  state[RUN]:

if (finished)   state[DONE] <= 1 ; else   state[RUN] <= 1 ;

  state[DONE]:

state[IDLE] <= 1 ;

out1 <= state[RUN] & ! finished ;

If you want to read more in depth about all of these points, including why one-hot is useful for high speed, read this longer writeup .

I arrived at the conclusions here on my own, but around the same time, Cliff Cummings presented a paper at SNUG San Jose 2003 that included these same points: Cliff's paper Cliff's website

Bayes Classifier VS Regression Function #

Consider the two-class classification problem with a label set given by $\mathcal{Y}=\{-1,1\}$, without loss of generality. The regression function for the binary variable $Y$ is given by $$\begin{align*} \mu(x)=&\mathbb{E}[Y\mid X=x]\\=&\mathbb{P}(Y=1\mid X=x)\cdot 1\\&+\mathbb{P}(Y=-1\mid X=x)\cdot (-1)\\=&\mathbb{P}(Y=1\mid X=x)\\&-\mathbb{P}(Y=-1\mid X=x).\end{align*} $$

The Bayes classifier becomes nothing else but the sign of the regression function

$$ \underset{y\in\{-1,1\}}{\operatorname{argmax}}~\mathbb{P}(Y=y\mid X=x) =\operatorname{sign}(\mu(x)) $$

except for the feature values at the decision boundary $\{x:\mu(x)=0\}$ for which we can arbitrarily assign the labels.

Multiple-Class Classification #

What if we have multiple labels, say, with $\mathcal{Y}=\{\mathcal{C}_1,\ldots,\mathcal{C}_K\}$ for some finite $K\geq 2$? Unfortunately, the sign trick above is insufficient to distinguish more than two classes. To handle more classes, we need to encode the categorical target using a vector of dummy variables.

One-Hot Encoding # The one-hot encoding of categorical target $Y\in \{\mathcal{C}_1,\ldots,\mathcal{C}_K\}$ is the vector given by $$(Y^{(1)},\ldots,Y^{(K)})\in \{0,1\}^K$$ with $$Y^{(k)}=\mathbf{1}[Y=\mathcal{C}_k],~1\leq k\leq K$$ where $\mathbf{1}[A]$ denotes the indicator function that equals to 1 if condition $A$ is satisfied and equals to 0 otherwise.

In this example, there are $K=3$ teams with labels A, B, and C. We convert each observation of the label A/B/C into a vector of 3 dummies.

The $K$-dimensional regression function for the one-hot encoded target is given by

$$\mu(x)=(\mu_1(x),\ldots,\mu_K(x))$$ where $$\begin{align*}\mu_k(x)=&\mathbb{E}[Y^{(k)}\mid X=x]\\=&\mathbb{P}\left( Y=\mathcal{C}_k\mid X=x\right).\end{align*}$$

With one-hot encoding, one can now estimate the Bayes classifier using a two-step procedure:

• First estimate the multivariate regression function $\mu(x)$
• Then choose the label $h(x)\in\{\mathcal{C}_1,\ldots,\mathcal{C}_K\}$ with largest regression value.

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vhdl code: one hot encoding of state

if I am using one hot encoding for the states and want to go from S0 -> S1 -> S2 -> S3 -> S0

Apparently the following code does this. However I am not sure how the state assignment part works in the snippet (comments mention rotation of 1 bit...?)... can someone please explain HOW this rotation works ie. why the "&state(2)" etc. It would also be extremely helpful if you could provide a simple hardware representation of the code snippet.

In the architecture we are told that S0 = 0001, S1 = 0010, S2 = 0100, S3 = 1000

• 1 \$\begingroup\$ There is no reason to be "clever" in your code writing. Write plainly and simply and let the tool optimize. Only when you are fighting for space should you start trying to code tricky like this. There is no value in state <= state(1 downto 0) & state(2) when a clearer and more easily understood case statement would get the same job done. \$\endgroup\$ –  akohlsmith Commented May 22, 2012 at 19:54

2 Answers 2

In practice, you will never explicitly use one hot encoding. Rather, you should design your VHDL file so that you use enumerations instead of explicit states. This allows the synthesis tools that you use to generate your design to come up with their own preferred encoding. In a CPLD, this would probably be dense coding, because gates are more abundant than flip flops. In an FPGA, this would probably be one hot, because flip flops are more abundant. In other random cases, the synther might think that gray coding, or sequential coding, might be better.

However, to answer your question, how does this perform a rotation? (note I am using your original 3-bit state, even though your question regards 4 bit states)

Consider state = "001". Thus, state(1 downto 0) = "01". Also, state(2) = '0'.

Thus, when you do state <= state(1 downto 0) & state(2), you are doing state <= "01" & '0'. This now means state = "010"; a left rotation by one bit.

In plain language, to rotate an n-bit vector to the left by one bit, take the lower n-1 bits, and concatenate the MSB on the right side of it. In this example, it's taking the state(1 downto 0) bits, and concatenating state(2) on the right side.

In contrast, a right rotation would be represented as state <= state(0) & state(2 downto 1). This takes the LSB, and then concatenates the upper n-1 bits on the right side of it. For state = "001", this right rotation would be like state <= '1' & "00". This now means state = "100".

I think the logic is wrong... you've got a four bit state vector, but you are only using three of the bits in any logic. It is obvious that to cycle through the states all you have to do is shift the bits left by one with rotation right? Just make a table showing the state sequence desired:

The hardware for this is just to wire the output of the 4-bit register back on itself with the lines crossed to get the affect above.

Namely: State(0) <= State(3), State(1) <= State(0), State(2) <= State(1), State(3) <= State(2)

The abbreviated way of stating that is to form a new vector from the old one like this:

Not sure my syntax is perfect, but that's the gist of it I believe; I think what I wrote is something like a Verilog/VHDL mashup. Anyway, you just want to express running the wires back to the right place so the 1 shifts left and around each clock.

As @mng noted - the '&' operator concatenates bit vectors together, and does not perform a logical-and, as one might think.

• \$\begingroup\$ how exactly is "--rotate state 1 bit to left" part doing the shifting? In terms of the vhdl syntax? \$\endgroup\$ –  rrazd Commented May 22, 2012 at 3:51
• 5 \$\begingroup\$ In VHDL, the '&' stands for concatenation. \$\endgroup\$ –  mng Commented May 22, 2012 at 4:58
• 1 \$\begingroup\$ @mng I like Verilog's syntax for this better... seems abusive to use & as an operator that doesn't correspond in some way to the 'and' logic operation; anyway yes the VHDL syntax is the key to what the OP was asking (the code is still wrong though) \$\endgroup\$ –  vicatcu Commented May 22, 2012 at 16:10
• \$\begingroup\$ @vicatcu: Seems abusive, because you're used to C. However the BASIC-like language are all consistent in use of AND for the bitwise operator and & for concatenation of strings. \$\endgroup\$ –  Ben Voigt Commented May 22, 2012 at 20:44
• \$\begingroup\$ And ultimately, VHDL's syntax is far cleaner: state <= state ROL 1; . Unfortunately the code in the question didn't use that. \$\endgroup\$ –  Ben Voigt Commented May 22, 2012 at 20:46

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One-Hot Encoding in Scikit-Learn with OneHotEncoder

• February 23, 2022 April 14, 2024

In this tutorial, you’ll learn how to use the OneHotEncoder class in Scikit-Learn to one hot encode your categorical data in sklearn . One-hot encoding is a process by which categorical data (such as nominal data) are converted into numerical features of a dataset. This is often a required preprocessing step since machine learning models require numerical data.

By the end of this tutorial, you’ll have learned:

• What one-hot encoding is and why it’s important in machine learning
• How to use sklearn’s OneHotEncoder class to one-hot encode categorical data
• How to one-hot encode multiple columns
• How to use the ColumnTransformer class to manage multiple transformations

Are you looking to one-hot encode data in Pandas? You can also use the pd.get_dummies() function for this!

Table of Contents

What is One-Hot Encoding?

One-hot encoding is the process by which categorical data are converted into numerical data for use in machine learning. Categorical features are turned into binary features that are “one-hot” encoded, meaning that if a feature is represented by that column, it receives a 1 . Otherwise, it receives a 0 .

This is perhaps better explained by an image:

You may be wondering why we didn’t simply turn the values in the column to, say, {'Biscoe': 1, 'Torgensen': 2, 'Dream': 3} . This would presume a larger difference between Biscoe and Dream than between Biscoe and Torgensen.

While this difference may exist, it isn’t specified in the data and shouldn’t be imagined.

However, if your data is ordinal , meaning that the order matters, then this approach may be appropriate. For example, when comparing shirt sizes, the difference between a Small and a Large is , in fact, bigger than between a Medium and a Large.

Why is One-Hot Encoding Important to Machine Learning?

Now that you understand the basic mechanics of one-hot encoding, you may be wondering how this all relates to machine learning. Because machine learning algorithms assume (and require) your data to be numeric, categorical data must be pre-processed in order for it to be accepted .

Following the example of the Island above – if we were to ask any classification or regression model to be built using the categorical data, an error would be raised. This is because machine learning algorithms cannot work with non-numerical data.

How to Use Sklearn’s OneHotEncoder

Sklearn comes with a one-hot encoding tool built-in: the OneHotEncoder class. The OneHotEncoder class takes an array of data and can be used to one-hot encode the data.

Let’s take a look at the different parameters the class takes:

Let’s see how we can create a one-hot encoded array using a categorical data column. For this, we’ll use the penguins dataset provided in the Seaborn library . We can load this using the load_dataset() function:

Let’s break down what we did here:

• We loaded the dataset into a Pandas DataFrame, df
• We initialized a OneHotEncoder object and assigned it to ohe
• We fitted and transformed our data using the .fit_transform() method
• We returned the array version of the transformed data using the .toarray() method

We can see that each of the resulting three columns are binary values. There are three columns in the array, because there are three unique values in the Island column. The columns are returned alphabetically.

We can access the column labels using the .categories_ attribute of the encoder:

If we wanted to build these columns back into the DataFrame, we could add them as separate columns:

In the next section, you’ll learn how to use the ColumnTransformer class to streamline the way in which you can one-hot encode data.

How to Use ColumnTransformer with OneHotEncoder

The process outlined above demonstrates how to one-hot encode a single column. It’s not the most intuitive approach, however. Sklearn comes with a helper function, make_column_transformer() which aids in the transformations of columns. The function generates ColumnTransformer objects for you and handles the transformations.

This allows us to simply pass in a list of transformations we want to do and the columns to which we want to apply them. It also handles the process of adding the data back into the original dataset. Let’s see how this works:

Let’s see what we did here:

• We imported the make_column_transformer() function
• The function took a tuple containing the transformer we want to apply and the column to which to apply to. In this case, we wanted to use the OneHotEncoder() transformer and apply it to the 'island' column.
• We used the remainder='passthrough' parameter to specify that all other columns should be left untouched.
• We then applied the .fit_transform() method to our DataFrame.
• Finally, we reconstructed the DataFrame

In the next section, you’ll learn how to use the make_column_transformer() function to one-hot encode multiple columns with sklearn.

How to One-Hot Encode Multiple Columns with Scikit-Learn

The make_column_transformer() function makes it easy to one-hot encode multiple columns. In the argument where we specify which columns we want to apply transformations to, we can simply provide a list of additional columns.

Let’s reduce our DataFrame a bit to see what this result will look like:

In this tutorial, you learned how to one-hot encode data using Scikit-Learn’s OneHotEncoder class. You learned what one-hot encoding is and why it matters in machine learning. You then learned how to use the OneHotEncoder class in sklearn to one-hot encode data. Finally, you learned how to use the make_column_transformer helper function for the ColumnTransformer class to one-hot encode multiple columns.

Additional Resources

To learn more about related topics, check out the tutorials below:

• Introduction to Scikit-Learn (sklearn) in Python
• Pandas get dummies (One-Hot Encoding) Explained
• K-Nearest Neighbor (KNN) Algorithm in Python
• Introduction to Random Forests in Scikit-Learn (sklearn)
• Official Documentation: OneHotEncoder

Nik Piepenbreier

Nik is the author of datagy.io and has over a decade of experience working with data analytics, data science, and Python. He specializes in teaching developers how to use Python for data science using hands-on tutorials. View Author posts

4 thoughts on “One-Hot Encoding in Scikit-Learn with OneHotEncoder”

This was very helpful. Thanks!

Thanks so much, Lealdo!

When I used all the imports from the code listings I still got unresolved functions:

AttributeError: ‘ColumnTransformer’ object has no attribute ‘get_feature_names’

Is this just because older versions of ColumTransformer had this function or is there some import not listed?

Sorry for the late reply, Louis! I have fixed the code to what is shown below. Thanks for catching this!

columns=transformer.get_feature_names_out()

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One-Hot Encoding in NLP

Natural Language Processing (NLP) is a quickly expanding discipline that works with computer-human language exchanges. One of the most basic jobs in NLP is to represent text data numerically so that machine learning algorithms can comprehend it. One common method for accomplishing this is one-hot encoding, which converts category variables to binary vectors. In this essay, we’ll look at what one-hot encoding is, why it’s used in NLP, and how to do it in Python .

One of the most basic jobs in natural language processing (NLP) is to describe written data numerically so that machine learning systems can comprehend it. One common method for accomplishing this is one-hot encoding, which converts category variables to binary vectors.

One-Hot Encoding:

One-hot encoding is the process of turning categorical factors into a numerical structure that machine learning algorithms can readily process. It functions by representing each category in a feature as a binary vector of 1s and 0s, with the vector’s size equivalent to the number of potential categories. 

Why One-Hot Encoding is Used in NLP:

• One-hot encoding is used in NLP to encode categorical factors as binary vectors, such as words or part-of-speech identifiers. 
• This approach is helpful because machine learning algorithms generally act on numerical data, so representing text data as numerical vectors are required for these algorithms to work.
• In a sentiment analysis assignment, for example, we might describe each word in a sentence as a one-hot encoded vector and then use these vectors as input to a neural network to forecast the sentiment of the sentence.

Suppose we have a small corpus of text that contains three sentences:

• Each word in these phrases should be represented as a single compressed vector. The first stage is to determine the categorical variable, which is the phrases’ terms. The second stage is to count the number of distinct words in the sentences to calculate the number of potential groups. In this instance, there are 17 potential categories.
• The third stage is to make a binary vector for each of the categories. Because there are 17 potential groups, each binary vector will be 17 bytes long. For example, the binary vector for the word “quick” will be [1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], with the 1s in the first and sixth places because “quick” is both the first and sixth group in the list of unique words.
• Finally, we use the binary vectors generated in step 3 to symbolize each word in the sentences as a one-hot encoded vector. For example, the one-hot encoded vector for the word “quick” in the first sentence is [1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], and the one-hot encoded vector for the word “seashells” in the second sentence is [0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0].

Python Implementation for One-Hot Encoding in NLP

Now let’s try to implement the above example using Python. Because finally, we will have to perform this programmatically else it won’t be possible for us to use this technique to train NLP models.

As you can see from the output, each word in the first sentence has been represented as a one-hot encoded vector of length 17, which corresponds to the number of unique words in the corpus. The one-hot encoded vector for the word “quick” is [0. 0. 0. 0. 0. 0. 0. 1. 0. 1. 0. 0. 0. 0. 0. 0. 1.].

Assume we have a text collection that includes three sentences:

• Each word in these phrases should be represented as a single compressed vector. We begin by identifying the categorical variable (the words in the sentences) and determining the number of potential groups (the number of distinct words in the sentences), which is 7 in this instance.
• Following that, we generate a binary array with a length of 7 for each group. Because “cat” is the first category in the collection of unique terms, the binary vector for the word will be [1, 0, 0, 0, 0, 0, 0].
• Finally, we use the binary vectors generated in the previous stage to symbolize each word in the sentences as a one-hot encoded vector. For example, in the first sentence, the one-hot encoded vector for the word “mat” is [0, 0, 0, 0, 0, 1], and in the second sentence, the one-hot encoded vector for the word “dog” is [0, 0, 1, 0, 0, 0].

This code initially generates a collection of unique words from the corpus, followed by a dictionary that translates each word into a number. It then iterates through the corpus, creating a binary vector with a 1 at the place corresponding to the word’s integer mapping and a 0 elsewhere for each word in each phrase. The resultant one-hot encoded vectors are displayed for each word in each phrase.

As can be seen, each word is represented as a one-hot encoded vector of length equal to the number of distinct words in the corpus. (which is 7 in this case). Each vector has a 1 in the place corresponding to the word’s integer mapping in the vocabulary set, and a 0 elsewhere.

Drawbacks of One-Hot Encoding in NLP

One of the major disadvantages of one-hot encoding in NLP is that it produces high-dimensional sparse vectors that can be extremely costly to process. This is due to the fact that one-hot encoding generates a distinct binary vector for each unique word in the text, resulting in a very big feature space. Furthermore, because one-hot encoding does not catch the semantic connections between words, machine-learning models that use these vectors as input may perform poorly. As a result, other encoding methods, such as word embeddings, are frequently used in NLP jobs. Word embeddings convert words into low-dimensional dense vectors that record meaningful connections between words, making them more useful for many NLP tasks.

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Ex-Yankees' Spark Plug Thriving With Mets During Hot Stretch

Joe najarian | jun 27, 2024.

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It goes without saying that the New York Mets are on a tear.

Having restored their record back to .500, the Mets have outscored their opponents 93-47 since June 12, scoring at least 10 runs five times over this stretch. What makes this offensive explosion so encouraging is that everyone is producing, 1 through 9.

That also includes "defense-first" outfielder Harrison Bader, who has been swinging a red-hot bat at the bottom of the lineup.

A New York native who spent the previous two seasons with the cross-town rival Yankees, the 30-year-old Bader signed a one-year, $10.5 million contract with the Mets during the offseason. He is widely known as one of the best defensive outfielders in the majors, winning a Gold Glove with the St. Louis Cardinals in 2021 and being worth 66 outs above average over the past six seasons , the best of any outfielder.

However, Bader has been more than just his glove with the Mets; as of Thursday, he has a 1.5 fWAR that is the third-highest on the team, only behind Francisco Lindor (3.2) and Brandon Nimmo (2.3). In 69 games this year, he's already surpassed his fWAR from 2023 (1.0 in 98 games) and matched his 2022 total (1.5 in 86 games). Bader's defense has remained excellent, being worth six outs above average with two defensive runs saved, but his offense is making him even more valuable.

Known as a free-swinger with fence-clearing pop, Bader currently has a .275 batting average (which would be a career-high) and a .743 OPS, with 20 extra-base hits (14 doubles and six home runs) and a 113 wRC+; the center fielder is just one homer shy of matching his total from last season.

Bader has been especially productive since June 12, the same date when the Mets started their hot streak; in 40 plate appearances, he has eight extra-base hits, nine runs scored, seven RBI, a .333/.350/.692 slash line, and a 194 wRC+. In the Subway Series on Tuesday and Wednesday, the eight-year veteran put on a show against his former team, going 4-for-9 and slamming a pair of home runs.

THESE GO TO 11. Second straight night with a home run for Harrison Bader! pic.twitter.com/hibcPaAizm — SNY (@SNYtv) June 27, 2024

Keep in mind that Bader is doing this while batting ninth in the lineup, providing surprising protection for a strong top of the order in Lindor, Nimmo, J.D. Martinez, and Pete Alonso. When the Mets are getting that kind of production from the bottom of the lineup, it's no wonder why they've been going wild offensively.

It's unknown if Bader can continue hitting above league average, as he's been very streaky throughout his career. But the Mets have to be ecstatic from what they've seen from the 30-year-old, as they not only got plus defense in center field: they got a complete ballplayer.

JOE NAJARIAN

Joe Najarian is a Rutgers University graduate from the Class of 2022. After an eight-month stint with Jersey Sporting News (JSN), covering Rutgers Football, Rutgers Basketball, and Rutgers Baseball, Najarian became a contributing writer on Inside the Pinstripes and Inside the Mets. He additionally writes on Giants Country, FanNation’s site for the New York Giants. Follow Joe on Twitter @JoeNajarian

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